Bipolar transistors are devices with two p-n junctions that are in close proximity to each other. A typical bipolar transistor has three device regions: an emitter, a collector, and a base disposed between the emitter and the collector. Ideally, the two p-n junctions, i.e., the emitter-base and collector-base junctions, are in a single layer of semiconductor material separated by a specific distance. Modulation of the current flow in one p-n junction by changing the bias of the nearby junction is called “bipolar-transistor action.”
If the emitter and collector are doped n-type and the base is doped p-type, the device is an “npn” transistor. Alternatively, if the opposite doping configuration is used, the device is a “pnp” transistor. Because the mobility of minority carriers, i.e., electrons, in the base region of npn transistors is higher than that of holes in the base of pnp transistors, higher-frequency operation and higher-speed performances can be obtained with npn transistor devices. Therefore, npn transistors comprise the majority of bipolar transistors used to build integrated circuits.
As the vertical dimensions of the bipolar transistor are scaled more and more, serious device operational limitations have been encountered. One actively studied approach to overcome these limitations is to build transistors with emitter materials whose band gaps are larger than the band gaps of the material used in the base. Such structures are called heterojunction transistors.
Heterostructures comprising heterojunctions can be used for both majority carrier and minority carrier devices. Among majority carrier devices, heterojunction bipolar transistors (HBTs) in which the emitter is formed of silicon (Si) and the base of a silicon-germanium (SiGe) alloy have recently been developed. The SiGe alloy (often expressed simply as silicon-germanium) is narrower in band gap than silicon.
Cut-off frequency (fT) and maximum oscillation frequency (fmax) are the most representative measures of operation speed for high-speed transistors. Hence, design and optimization efforts for high-speed transistors are mostly directed toward optimization of these two parameters. One of the device parameters that influences fT and fmax is the base to collector capacitance (Ccb). As is known to those skilled in the art, Ccb contributes to fT as a form of RC delays associated with emitter and collector resistance and transconductance. The base to collector capacitance contribution to fmax dominates over those from any other parameter since its effect on fmax are two-folded: one directly affects fmax, while the other comes indirectly from fT. Another device parameter that influences fmax is the base resistance Rb. The raised extrinsic base region in modern bipolar transistor is composed mostly of polycrystalline silicon, which has lower mobility compared to crystalline silicon. For such device structure, Rb is limited by the lower charge carrier mobility in polycrystalline silicon.
More than two-thirds of the total Ccb comes from the extrinsic portion, or parasitic capacitance. This parasitic capacitance results from the overlap between the collector and base (intrinsic and extrinsic) regions outside the active transistor area and enclosed by a shallow trench isolation (STI). The overlap between these regions can not be minimized by lithography due to limitation of overlay and alignment tolerances. Moreover, the capacitance is further increased by the transport enhanced diffusion of the dopants from the base region to the collector region. Therefore, structural optimization of the device that reduces the parasitic component is a key factor for the improvement of fT and fmax (i.e., the operational speed of the device). In addition, Rb is limited by the extrinsic base resistance, which is mostly composed of polycrystalline silicon. The major charge carrier mobility in polycrystalline silicon is considerably lower than in crystalline silicon.
U.S. Pat. No. 5,599,723 to Sato entitled “Method for Manufacturing Bipolar Transistor Having Reduced Base-Collector Parasitic Capacitance” discloses the use of SiGe for the base, and that the parasitic capacitance formed between the collector epitaxial layer and the base electrode single crystal silicon film is reduced because the distance between them is set to about 1000 Å. In order to reduce the parasitic capacitance by the prior art technique, the intrinsic base must be thickened, and thus the cut-off frequency fT is lowered. A single crystal form of silicon formed by the selective epitaxial growth is used for the base electrode to reduce the parasitic capacitance between the base and the collector, particularly by forming the base of SiGe. The entire device including the collector region is formed above the surface of the silicon semiconductor substrate. This approach to reducing the parasitic capacitance is to use selective epitaxy to grow the intrinsic base.
U.S. Pat. No. 5,128,271 to Bronner et al. entitled “High Performance Vertical Bipolar Transistor Structure via Self-aligning Processing Techniques” describes a self-aligned, vertical bipolar transistor structure and a method of manufacturing such a structure with “reduced parasitic base collector capacitance” achieved by providing correct alignment. The Bronner et al. approach has similarities with the present approach to solution of the parasitic base collector capacitance problem. However, the approach of this invention has significant features not described in the Bronner et al. patent. For example, the present invention decouples the primary shallow trench isolation formation from the secondary shallow isolation formation to reduce the parasitics. This major difference allows a robust manufacturing process and flexible device performance.
U.S. Pat. No. 6,864,560 to Khater et al. entitled “Bipolar Transistor Structure With a Shallow Isolation Extension Region Providing Reduced Parasitic Capacitance” discloses a structural modification to a bipolar transistor that reduces the parasitic component of Ccb. More specifically, Khater et al. discloses partially removing the excess overlap region between the collector and the base and filling that same with a dielectric prior to forming the extrinsic base region. The dielectric separates the collector from the extrinsic base and acts as a barrier for dopant diffusion to reduce the parasitic component of Ccb. Although Khater et al. discloses the use of a dual shallow trench isolation scheme, the present invention improves upon the previous technology by providing a second shallow trench isolation that has sloped sidewalls positioned adjacent the collector region. The sloped sidewalls of the second trench isolation region of the present invention gives maximum Ccb close to the junction, but keeps the collector region sufficiently wide such that the collector resistance is kept low.
Moreover, the present invention provides an extended secondary shallow trench isolation that overlaps the whole raised extrinsic base region, which allows, in some embodiments of the present invention, the raised extrinsic base region to be completely composed of monocrystalline silicon. In this case, Rb is reduced due to a higher mobility in the crystalline raised extrinsic base. Furthermore, the mobility in the base can be further improved by a stress layer.
In view of the above, there is a need for providing a bipolar transistor wherein structural modifications have been introduced which reduces the parasitic component of Ccb and Rb with minimum adverse effect on other parameters. The parasitic component of Ccb in typical silicon based bipolar transistors is the result of the existence of a depletion region of the base-collector p-n junction formed at the extrinsic part of the device. In accordance with the present invention, the parasitic capacitance is reduced by employing materials with reduced dielectric constants in the depletion region, since silicon has a high dielectric constant.